Fin Field Effect Transistors (FinFETs) are becoming increasingly attractive due to their good control of short channel effects. FIG. 1 is a perspective view schematically showing a FinFET by way of example. As shown in FIG. 1, the FinFET comprises a bulk Si substrate 100, a fin 101 formed on the bulk Si substrate 100, a gate stack 102 crossing the fin 101 and including, for example, a gate dielectric layer and a gate electrode layer (not shown), and an isolation layer (e.g., SiO2) 103. In this FinFET, under the control of the gate electrode, conductive channels are formed in the fin 101, and specifically, in three side surfaces (i.e., a left side surface, a right side surface, and a top side surface as shown in the figure) of the fin 101. That is, a portion of the fin 101 under the gate electrode serves as a channel region, and source and drain regions are located at both sides of the channel region, respectively.
In the example shown in FIG. 1, the FinFET is formed on the bulk semiconductor substrate. Alternatively, a FinFET can be formed on other types of substrate such as a Semiconductor On Insulator (SOI) substrate. Furthermore, the FinFET shown in FIG. 1 has the channel formed in all the three side surfaces of the fin 101, and thus is referred to as a 3-gate FinFET. On the other hand, a 2-gate FinFET can be formed by, for example, providing an isolation layer (e.g., nitride) between the top surface of the fin 101 and the gate stack 102, in which case the top surface of the fin 101 will not be subject to the control of the gate electrode and thus will have no channel formed therein.
In the following, a conventional flow for manufacturing a FinFET is described with reference to FIGS. 2(a)-2(f).
As shown in FIG. 2(a), a bulk Si semiconductor layer 100 is provided, and an oxide (silicon oxide) layer 104 and a nitride (silicon nitride) layer 105 are formed sequentially thereon. For example, the oxide layer 104 may have a thickness of about 2-5 nm, and the nitride layer 105 may have a thickness of about 10-50 nm. The oxide layer 104 and the nitride layer 105 can sever as a hard mask layer in a later process. Further, a layer of patterned photo resist 106 is formed on the nitride layer 105. The patterned photo resist 106 is positioned where a fin is to be formed.
Next, as shown in FIG. 2(b), the hard mask layer (including the nitride layer 105 and the oxide layer 104) is patterned. Specifically, the nitride layer 105 is etched by means of, for example, Reactive Ion Etching (RIE), using the patterned photo resist 106 as a mask. The etching can be stopped on the oxide layer 104. Then, the oxide layer 104 is further etched by means of, for example, RIE, resulting in the patterned hard mask layer 104, 105. Finally, the photo resist 106 is removed.
Then, as shown in FIG. 2(c), the semiconductor layer 100 is patterned by means of, for example, RIE, using the patterned hard mask layer 104, 105 as a mask, to form a fin 101 on the semiconductor layer 100. Here, the height of the fin 100 may be controlled by setting process parameters during RIE, such as etching time and the like.
After the formation of the fin, as shown in FIGS. 2(d) and 2(e), an isolation layer is formed on both sides of the fin 101 over the semiconductor layer 100. Specifically, as shown in FIG. 2(d), firstly an oxide layer 103, such as a High Density Plasma (HDP) oxide layer (e.g., SiO2), is deposited on the entire arrangement. The oxide layer 103 has its bottom portions thicker than its portions on side walls of the fin 101. Then, as shown in FIG. 2(e), the oxide layer 103 is etched isotropically to expose the side walls of the fin 101, resulting in the isolation layer 103.
Subsequently, as shown in FIG. 2(f), a gate dielectric layer 102-1 and a gate electrode layer 102-2 are formed to cross the fin 101, and thus constitutes a gate stack. After that, the process can proceed conventionally, to manufacture source/drain regions, metal interconnections to finish a final device.
In the above conventional process, the height of the fin 101 may be controlled by means of the etching process parameters during the patterning of the fin 101, and thus the channel width of the final device can be controlled. However, in this way the fin height is indirectly controlled by means of the process parameters, without direct control on the fin height. Therefore, such control is not sufficiently accurate.
Therefore, there is a need for a semiconductor device and a method for manufacturing the same, by which it is possible to control a height of a fin in a more accurate way.